1. Field of the Invention
The present invention relates to manufacturing small dimension features of objects, such as integrated circuits, using photolithographic masks. More particularly, the present invention relates to the application of phase shift masking to complex layouts for integrated circuits and similar objects.
2. Description of Related Art
Phase shift masking, as described in U.S. Pat. No. 5,858,580, has been applied to create small dimension features in integrated circuits. Typically the features have been limited to selected elements of the design, which have a small, critical dimension. Although manufacturing of small dimension features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more extensively in the manufacturing of such devices. However, the extension of phase shift masking to more complex designs results in a large increase in the complexity of the mask layout problem. For example, when laying out phase shift areas on dense designs, phase conflicts will occur. One type of phase conflict is a location in the layout at which two phase shift regions having the same phase are laid out in proximity to a feature to be exposed by the masks, such as by overlapping of the phase shift regions intended for implementation of adjacent lines in the exposure pattern. If the phase shift regions have the same phase, then they do not result in the optical interference necessary to create the desired effect. Thus, it is necessary to prevent inadvertent layout of phase shift regions in phase conflict.
Another problem with laying out complex designs which rely on small dimension features, arises because of isolated exposed spaces which may have narrow dimension between unexposed regions or lines.
Because of these and other complexities, implementation of a phase shift masking technology for complex designs will require improvements in the approach to the design of phase shift masks, and new phase shift layout techniques.